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New Capabilities for Verilog-A Implementations of Compact Device Models

M. Mierzwinski, P. OHalloran, B. Troyanovsky, K. Mayaram and R.W. Dutton
Tiburon Design Automation, US

Keywords: Analog, Compact Model, Simulation, Verilog-A

Acceptance of a model requires its availability in main-stream simulators, yet it can be difficult to get a new model into commercial simulators. In this paper we present simulation results using a compiled Verilog-A architecture implemented in commercial simulators. We demonstrate industry standard models, including BSIMSOI and BSIM3, as well as new MEMS models coupled into both complex harmonic balance and device level simulators. This is the first demonstration of multiple commercial simulators sharing the same model binaries. The architecture is engineered to be easily embedded into existing analog simulation engines and is currently being deployed in such environments as UC Berkeley SPICE, Agilent Technologies RF/MW design environments (ADS and RFDE), Eaglewares GENESYS simulator product, in addition to other industry-proprietary and academic simulation engines such as Oregon State Universitys CODECS. The ability to model at high levels of abstraction in Verilog-A, as well as to efficiently simulate complex transistor models, allows developers to easily shift between physical, compact, and abstract model domains. The implementation described here provides a Verilog-A OVI 2.0 compliant solution in commercial products with simulation speeds close to that of traditional C-based models. For the first time, model developers now have a convenient development and release process.

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