Nano Science and Technology InstituteNano Science and Technology Institute
Nano Science and Technology Institute 2004 NSTI Nanotechnology Conference & Trade Show
Nanotech 2004
BioNano 2004
Program
Topics & Tracks
Sunday
Monday
Tuesday
Wednesday
Thursday
Index of Authors
Keynotes
Awards
Tutorials
Business & Investment
2004 Sub Sections
Sponsors
Exhibitors
Venue 2004
Proceedings
Organization
Press Room
Purchase CD/Proceedings
NSTI Events
Subscribe
Site Map
Nanotech Proceedings
Nanotechnology Proceedings
Supporting Organizations
Nanotech Supporting Organizations
Media Sponsors
Nanotech Media Sponsors
Event Contact
696 San Ramon Valley Blvd., Ste. 423
Danville, CA 94526
Ph: (925) 353-5004
Fx: (925) 886-8461
E-mail:
 
 

Novel Approach to Circuit Board Testing

R.G. Wright, L.V. Kirkland, M. Zgol, D. Adebimpe, E. Keenan and R. Mulligan
GMA Industries, Inc., US

Keywords: molecular electronics, carbon nanotubes, bed of nails, circuit board testing

Abstract:
Fast, accurate, and inexpensive identification of failed integrated circuits on electronic circuit boards presents a major challenge for the electronic testing industry. In this paper we describe research and development efforts in the application of nanoscale sensors to implement an original method for bed-of-needles testing for printed circuit boards testing. This approach performs functional testing that eliminates the need to have a pre-existing model of a circuit board while automating much of the development process. The general concept involves creating arrays of nanoscale sensor probes, using molecular electronics for incorporating test instruments and computing logic for test interpretation directly into a pod consisting of multiple nails, and distributing these pods across the face and back of a circuit card using a contact fixture. The resulting test approach exhibits massive parallelism combined with extremely compact size that facilitates novel testing approaches not possible with current generation or planned architecture test equipment. Many existing limitations resulting from diminished scale of electronic devices that make it harder to test these devices are overcome, while improving overall test speed and accuracy by placing the test instruments and computing power directly at the device and pins being tested.

Nanotech 2004 Conference Technical Program Abstract

 
Sponsors
Nanotech Sponsors
News Headlines
NSTI Online Community
 
 

© Nano Science and Technology Institute, all rights reserved.
Terms of use | Privacy policy | Contact