Gate Length Scaling Effects in ESD Protection Ultra-thin Body SOI Devices
J-W Lee, Y. Li and S.M. Sze
Natl Nano Device Labs & Natl Chiao Tung Univ, TW
Keywords: ESD, ultra-thin body, SOI, gate length scaling effects
In this paper we experimentaly explore the gate length scaling effects which related to the abrupt degation of electrostatic discharge (ESD) robustness for ultra-thin body silicon on insulator (SOI) devices and integrated circuits (ICs). It is found that, for the ultra-thin body SOI, the ESD protection devices fail when the gate length of protection devices is smaller than the 0.18 um. Taking the effects into consideration, it is believed that optimizations among the device profiles, geometries, and the protection efficiency should be done simultaneously for high performance VLSI circuit design, in particular for modern System-on-chip (SOC). This observation is useful to both the nano-scale CMOS fabrication technology and VLSI circuit design.
Nanotech 2004 Conference Technical Program Abstract