Pareto-Optimal Modeling for Efficient PLL Optimization
S.K. Tiwary, S. Velu, R.A. Rutenbar, T. Mukherjee
Carnegie Mellon University, US
Keywords: behavioral modeling, pareto-optimal design, analog circuits, phase locked-loop, circuit optimization
Simulation-based synthesis tools for analog circuits [1,2] face a problem extending their sizing/biasing methodology to larger block-level designs such as phase lock loops or converters: the time to fully evaluate (i.e., to fully simulate) each complete circuit solution candidate is prohibitive inside a numerical optimization loop. In this paper, we show how to circumvent this problem with a careful mix of behavioral models for less-critical parts of the block, and pareto-optimal trade-off models for the critical components. In particular, we show how to adapt current circuit synthesis techniques to build the required tradeoff models. As a concrete example of the methodology, we show detailed simulation results from the synthesis of critical portions of a 500MHz digital frequency synthesizer PLL.
Nanotech 2004 Conference Technical Program Abstract