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2004 Workshop on Compact Modeling

Workshop on Compact Modeling

in collaboration with

Seventh International Conference on
Modeling and Simulation of Microsystems

March 7-11, 2004
Boston Sheraton Hotel & Copley Convention Center
Boston, Massachusetts, U.S.A.

Home|Synopsis|Invitees|Program|Poster|Tutorial|Slides|Website
Date
March 9-11, 2004
Venue Boston Sheraton Hotel & Copley Convention Center
Boston, Massachusetts, USA

Synopsis Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design over the past decades, and are playing an ever increasingly important role in the nanometer system-on-chip (SOC) era.  As the mainstream MOS technology is scaled into the nanometer regime, development of a truly physical and predictive compact model for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge.

Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together.  The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors.  For WCM-MSM2004, it is planned to have an Invited-Speaker Session, a contributed Poster Session, as well as a Tutorial Session.  The topics cover all important aspects of compact model development and deployment, within the main theme - compact models for circuit simulation:

  • Bulk MOS intrinsic models
  • SOI/double-gate/floating-gate MOS models
  • Bipolar/HBT/SiGe/GaN/JFET models
  • RF/noise/scalable capacitance/NQS models
  • Statistical/predictive/process-based models
  • Interconnection/passive device models
  • Extrinsic/parasitic element models
  • Reliability/hot carrier/tunneling/ESD models
  • Atomic-level/quantum-mechanical compact models
  • Numerical/TCAD/behavioral/table-based models
  • Model parameter extraction and optimization
  • Model-simulator interface and standardization
Invited Speakers Invited speakers from all over the world (11 countries) are listed below:
  • Narain Arora, Cadence Design Systems, USA
  • Matthias Bucher, Technical University of Crete, Greece
  • Mansun Chan, Hong Kong University of Science and Technology, Hong Kong
  • Yuhua Cheng, Skyworks Solutions, USA
  • Jamal Deen, McMaster University, Canada
  • Robert Dutton, Stanford University, USA
  • Carlos Galup-Montoro, Universidade Federal de Santa Catarina, Brazil
  • Dirk Klaassen, Philips Research Laboratories, The Netherlands
  • Shiuh-Wuu Lee, Intel, USA
  • Juin Liou, University of Central Florida, USA
  • Colin McAndrew, Motorola, USA
  • James Meindl, Georgia Institute of Technology, USA
  • Mitiko Miura-Mattausch, Hiroshima University, Japan
  • Paolo Pavan, Università di Modena e Reggio Emilia, Italy
  • Michael Schroter, University of Technology Dresden, Germany
  • Michael Shur, Rensselaer Polytechnic Institute, USA
  • Xuemei Xi, University of California at Berkeley, USA
  • Zhiping Yu, Tsinghua University, China
  • Xing Zhou, Nanyang Technological University, Singapore
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Workshop
Program
There are 19 invited papers, which are categorized in the following topic areas (speakers underlined):

Advanced device models (SiGe, GaN, Ballistic MOS):

  • Technology Limits and Compact Model for SiGe Scaled FETs
    R. W. Dutton and Chang-Hoon Choi, Stanford University, US
  • Compact Models for AlGaN/GaN MOS Devices
    M. S. Shur, G. Simin, A. Khan, and R. Gaska, Rensselaer Polytechnic Institute, US
  • Ballistic MOS Model (BMM) Considering Full 2D Quantum Effects
    Z. Yu, D. Zhang, and L. Tian, Tsinghua University, CN
Bulk MOS intrinsic models:
  • Geometry- and Bias-Dependence of Normalized Transconductances in Deep Submicron CMOS
    M. Bucher, D. Kazazis*, F. Krummenacher**, Technical University of Crete, GR, *Brown University, US, **Swiss sFederal Institute of Technology, Lausanne, CH
  • Self-Consistent DC, AC, Noise and Mismatch for the MOSFET
    C. Galup-Montoro, M. C. Schneider, A. Arnaud, and H. Klimach, Universidade Federal de Santa Catarina, BR
  • Recent Enhancements of MOS Model 11
    R. van Langevelde, A. J. Scholten, and D. B. M. Klaassen, Philips Research Laboratories, NL
  • Noise Modeling with HiSIM Based on Self-Consistent Surface-Potential Description
    M. Miura-Mattausch, S. Hosokawa, D. Navarro, S. Matsumoto, H. Ueno, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, T. Kage, and S. Miyamoto, Hiroshima University, JP
  • The Development of Next Generation BSIM for Sub-100nm Mixed-Signal Circuit Simulation
    X. Xi, J. He, M. Dunga, C.-H. Lin, B. Heyderi, H. Wan, M. Chan, A. M. Niknejad, and C. Hu, University of California at Berkeley, US
  • Unified Regional Approach to Consistent and Symmetric DC/AC Modeling of Deep-Submicron MOSFETs
    X. Zhou, S. B. Chiah, K. Chandrasekaran, K. Y. Lim*, L. Chan*, and S. Chu*, Nanyang Technological University, *Chartered Semiconductor Manufacturing, SG
Interconnect models:
  • Modeling and Characterization of Wire Inductance for High Speed VLSI Design
    N. D. Arora and L. Song, Cadence Design Systems, US
  • Emerging Challenges in Compact Modeling
    S.-W. Lee, P. Packan, C. Dai, and N. Hakim, Intel, US
Passive device models:
  • R3, an Accurate JFET and 3-Terminal Diffused Resistor Model
    C. McAndrew, Motorola, US
RF/noise models:
  • Advanced MOSFET Modeling for RF IC Design
    Y. Cheng, Skyworks Solutions, US
  • RF Noise Models of MOSFETs – A Review
    S. Asgaran and M. Jamal Deen, McMaster University, CA
Bipolar models:
  • Bias Dependent Modeling of Collector-Base Junction Effects in Bipolar Transistors
    M. Schroter and H. Tran, University of Technology Dresden, DE
Double-gate MOS models:
  • Quasi-2D Compact Modeling for Double-Gate MOSFET
    M. Chan, T. Y. Man, J. He*, X. Xi*, C.-H. Lin*, X. Lin, P. K. Ko, A. M. Niknejad, and C. Hu*, Hong Kong University of Science and Technology, HK, *University of California at Berkeley, US
  • Compact, Physics-Based Modeling of Nanoscale Limits of Double-Gate MOSFETs
    Q. Chen, L. Wang, R. Murali, and J. D. Meindl, Georgia Institute of Technology, US
Floating-gate MOS models:
  • Floating Gate Devices: Operation and Compact Modeling
    P. Pavan, L. Larcher, and A. Marmiroli, Università di Modena e Reggio Emilia, IT
ESD models:
  • Compact MOSFET Model for ESD Applications
    J. J. Liou and X. Gao, University of Central Florida, US
Poster Session Poster presentations in the scope of "compact models for circuit simulation" are solicited.  A 10-minute oral briefing for each poster paper is planned before the poster presentation session.  Contributed poster papers are listed below (presenters underlined):
  • A Non-Charge-Sheet Analytical Theory of Undoped Symmetric Double-Gate MOSFETs from the Exact Solution of Poisson's Equation using SPP Approach
    J. He, X. Xi, C.-H. Lin, M. Chan, A. Niknejad, and C. Hu, University of California at Berkeley, US
  • An Exact Analytical Model of Undoped Body MOSFETs using the SPP Approach
    J. He, X. Xi, M. Chan, A. Niknejad, and C. Hu, University of California at Berkeley, US
  • Linear Cofactor Difference Extrema of MOSFET's Drain Current and Their Application in Parameter Extraction
    J. He, X.Xi, M. Chan, A. Niknejad, and C. Hu, University of California at Berkeley, US
  • Threshold-Voltage-Based Regional Modeling of MOSFETs with Symmetry and Continuity
    S. B. Chiah, X. Zhou, K. Chandrasekaran, K. Y. Lim*, L. Chan*, and S. Chu*, Nanyang Technological University, *Chartered Semiconductor Manufacturing, SG
  • Physics-Based Scalable Threshold-Voltage Model for Strained-Silicon MOSFETs
    K. Chandrasekaran, X. Zhou, and S. B. Chiah, Nanyang Technological University, SG
  • An Analytical Subthreshold Current Model for Ballistic Double-Gate MOSFETs
    J. L. Autran, D. Munteanu, O. Tintori, M. Aubert, and E. Decarre, Laboratoire Matériaux et Microélectronique de Provence, FR
  • Quantum-Mechanical Analytical Modeling of Threshold Voltage in Long-Channel Double-Gate MOSFET with Symmetric and Asymmetric Gates
    J. L. Autran, D. Munteanu, O. Tintori, S. Harrison*, E. Decarre, and T. Skotnicki*, Laboratory for Materials and Microelectronics of Provence, *STMicroelectronics, FR
  • Improved Compact Model for Four-Terminal DG MOSFETs
    T. Nakagawa, T. Sekigawa, T. Tsutsumi*, M. Hioki, E. Suzuki, and H. Koike, National Institute of Advanced Industrial Science and Technology, *Meiji University, JP
  • Predicting the SOI History Effect Using Compact Models
    M. H. Na, J. S. Watts, E. J. Nowak, R. Q. Williams, and W. F. Clark, IBM, US
  • New Capabilities for Verilog-A Implementations of Compact Device Models
    M. Mierzwinski, P. O’Halloran, B. Troyanovsky, K. Mayaram*, and R. W. Dutton**, Tiburon Design Automation, *Oregon State University, **Stanford University, US
  • A Practical Method to Extract Extrinsic Parameters for the Silicon MOSFET Small-Signal Model
    S.-C. Wang, G.-W. Huang, K.-M. Chen, H.-C. Tseng*, and T.-L. Hsu*, National Nano Device Laboratories, *United Microelectronics Corporation, TW
  • Automatic BSIM3/4 Model Parameter Extraction with Penalty Functions
    Y. Mahotin and E. Lyumkis, Integrated Systems Engineering, US
  • A Trial Report: HiSIM-1.2 Parameter Extraction for 90 nm Technology
    Y. Iino, Silvaco Japan, JP
  • Extraction of Extrinsic Series Parameter in RF CMOS
    M. S. Alam* and G. A. Armstrong, The Queen’s University of Belfast, UK, *AMU, IN
  • Analytic Formulae for the Impact Ionization Rate for Use in Compact Models of Ultra-Short Semiconductor Devices
    H. Morris*, M. M. De Pass**, and H. Abebe, USC Information Sciences Institute, *San Jose State University, **Claremont Graduate University, US
  • On the Correlations Between Model Process Parameters in Statistical Modeling
    J. Slezák, A. Litschmann, S. Banáš, R. Mlcoušek, and M. Kejhar, ON Semiconductor, CZ
  • Characterization and Modeling of Silicon Tapered Inductors
    A. S. Peng, K. M. Chen, G. W. Huang, H. Y. Chen*, and C. Y. Chang*, National Nano Device Laboratories, *National Chiao Tung University, TW
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Tutorial Session Two tutorials are offered as listed below:
  • Review of the EKV3.0 MOSFET Model
    Matthias Bucher, Technical University of Crete, Greece
  • RF CMOS: Current Status and Compact Modeling
    Juin Liou, University of Central Florida, USA
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Presentation
Slides
(Click on each  to download the PDF file.  © Copyright of the PDF files belongs to the respective contributors.  Last update: April 20, 2004.)
Download and save ...Download and save the entire ZIP file of presentation slides (20MB)

View SlidesXing Zhou, Openning Remark


Invited papers View SlidesRobert Dutton, Technology Limits and Compact Model for SiGe Scaled FETs
View SlidesMichael Shur, Compact Models for AlGaN/GaN MOS Devices
View SlidesZhiping Yu, Ballistic MOS Model (BMM) Considering Full 2D Quantum Effects
View SlidesMatthias Bucher, Geometry- and Bias-Dependence of Normalized Transconductances in Deep Submicron CMOS
View SlidesCarlos Galup-Montoro, Self-Consistent DC, AC, Noise and Mismatch for the MOSFET
View SlidesDirk Klaassen, Recent Enhancements of MOS Model 11
View SlidesMitiko Miura-Mattausch, Noise Modeling with HiSIM Based on Self-Consistent Surface-Potential Description
View SlidesXing Zhou, Unified Regional Approach to Consistent and Symmetric DC/AC Modeling of Deep-Submicron MOSFETs
View SlidesShiuh-Wuu Lee, Emerging Challenges in Compact Modeling
View SlidesColin McAndrew, R3, an Accurate JFET and 3-Terminal Diffused Resistor Model
View SlidesYuhua Cheng, Advanced MOSFET Modeling for RF IC Design
View SlidesJamal Deen, RF Noise Models of MOSFETs – A Review
View SlidesMichael Schroter, Bias Dependent Modeling of Collector-Base Junction Effects in Bipolar Transistors
View SlidesMansun Chan, Quasi-2D Compact Modeling for Double-Gate MOSFET
View SlidesQiang Chen, Compact, Physics-Based Modeling of Nanoscale Limits of Double-Gate MOSFETs
View SlidesPaolo Pavan, Floating Gate Devices: Operation and Compact Modeling
View SlidesJuin Liou, Compact MOSFET Model for ESD Applications

Posters View SlidesJin He, A Non-Charge-Sheet Analytical Theory of Undoped Symmetric Double-Gate MOSFETs from the Exact Solution of Poisson's Equation using SPP Approach
View SlidesJin He, An Exact Analytical Model of Undoped Body MOSFETs using the SPP Approach
View SlidesJin He, Linear Cofactor Difference Extrema of MOSFET's Drain Current and Their Application in Parameter Extraction
View SlidesKarthik Chandrasekaran, Threshold-Voltage-Based Regional Modeling of MOSFETs with Symmetry and Continuity
View SlidesKarthik Chandrasekaran, Physics-Based Scalable Threshold-Voltage Model for Strained-Silicon MOSFETs
View SlidesT. Nakagawa, Improved Compact Model for Four-Terminal DG MOSFETs
View SlidesMarek Mierzwinski, New Capabilities for Verilog-A Implementations of Compact Device Models
View SlidesSheng-Chun Wang, A Practical Method to Extract Extrinsic Parameters for the Silicon MOSFET Small-Signal Model
View SlidesYuri Mahotin, Automatic BSIM3/4 Model Parameter Extraction with Penalty Functions
View SlidesYoshihisa Iino, A Trial Report: HiSIM-1.2 Parameter Extraction for 90 nm Technology
View SlidesHenok Abebe, Analytic Formulae for the Impact Ionization Rate for Use in Compact Models of Ultra-Short Semiconductor Devices
View SlidesJirí Slezák, On the Correlations Between Model Process Parameters in Statistical Modeling

Tutorials View SlidesMatthias Bucher, Review of the EKV3.0 MOSFET Model
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Websites for Proceedings http://www.nsti.org/procs/Nanotech2004v2/3
(Vol. 2, Chapter 3: Compact Modeling)

WCM-MSM2004
official websites
http://www.nsti.org/Nanotech2004/WCM2004
WCM2003 website View 2003 WCM program and presentation slides
WCM2002 website View 2002 WCM program and presentation slides
Download PDFClick to download the program (PDF) (Updated: April 11, 2004) 
 
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