Modeling of Direct Tunneling Current in Multi-Layer Gate Stacks
Mohan V. Dunga, Xuemei Xi, Jin He, I. Polishchuk, Qiang Lu, Mansun Chan, Ali Niknejad, and Chenming Hu
Department of Electrical Engineering and Computer Science, UC Berkeley, US
Keywords: Gate Stack, Direct Tunneling
Device scaling to improve performance calls for reduction of the gate oxide thickness but at a cost of increased direct tunneling gate current. The ITRS 2001 recognizes the need of gate scaling below 2nm and hence the use of high-k dielectric gate stacks to reduce gate leakage. It also recognizes the need of gate stack models for ultra-thin dielectrics to help the design of dielectric stacks. Numerical methods exist to solve for direct tunneling through dielectric stacks using Schrödinger’s equation. In this work, a simple analytical model for direct tunneling gate leakage in multi-layer gate stacks is developed. Theoretical derivation is done to show that the current BSIM equation for direct tunneling gate current through a single layer also works for the multi-layer case. Experimental data from devices with a stack of HfO2 and SiO2 and a stack of HfO2 and oxynidtride was used to verify the model.
NSTI Nanotech 2003 Conference Technical Program Abstract