MOS Transistor Modeling for RF Integrated Circuit Design
Workshop on Compact Modeling Tutorial
Prof. Christian Enz
The design of radio-frequency (RF) integrated circuits in deep-submicron
CMOS processes requires accurate and scalable compact models of the MOS
transistor that are valid in the GHz frequency range and beyond.
Unfortunately, the currently available compact models give inaccurate
results if they are not modified adequately. This lecture presents the basis
of the modeling of the MOS transistor for circuit simulation at RF. A
physical and scalable equivalent circuit that can easily be implemented as a
Spice subcircuit is described. The small-signal, noise and large-signal
operations are discussed and measurements made on a 0.25 um CMOS process are
presented that validate the RF MOS model up to 10 GHz.
Table of Contents
- CMOS technology evolution: evolution of CMOS processes, process scaling, low-voltage constraint and its impact to RF CMOS circuit design.
- Small-signal modeling: long-channel intrinsic small-signal parameters and their bias dependence, transcapacitances and non-quasistatic (NQS) effects, short-channel effects on small-signal parameters, extrinsic components (junction capacitances, series resistances, overlap capacitances), intra-device substrate coupling, y-parameters, ft and fmax, non-quasistatic versus quasistatic.
- Noise modeling: thermal noise model, noise in short-channel devices, noise at HF, induced gate noise, HF noise parameters and their dependence on device geometry.
- Large-signal modeling: evaluation of large-signal models at RF.