Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together.  The objective is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers and circuit designers.  It consists of a 2 day Invited-Speaker Session, an Evening Panel Session, and a Tutorial Session.  Regular papers are also solicited to follow the above sessions in the Contributed-Paper Session.  The topics are centered at bulk-Si and SOI MOSFET compact models for circuit simulation to address the following issues:

• Physics-based I-V model formulations
• Scalable AC/RF/noise models
• Predictive models with process correlation
• Statistical modeling with compact models
• Compact model with higher-order (atomic-level) effects
• Parameter extraction
• Global vs local optimization
• Equivalent circuit generation from numerical simulation
• Compact solution from surface-potential-based models
• Benckmark tests and model comparisons
• Compact models for SOI MOSFETs
• Interconnect modeling in CMOS technology
• Role of CM in bridging technology development, TCAD, and circuit design
• Trends and needs in compact models in the VDSM era

• Narain Arora, Simplex Solutions, USA
• Peter Bendix, LSI Logic, USA
• Britt Brooks, Texas Instruments, USA
• Matthias Bucher, National Technical University of Athens, Greece
• Mansun Chan, Hong Kong University of Science and Technology, Hong Kong
• Jamal Deen, McMaster University, Canada
• Michael Duane, Applied Materials, USA
• Christian Enz, Swiss Center for Electronics and Microtechnology, Switzerland
• Jerry Fossum, University of Florida, USA
• Daniel Foty, Gilgamesh Associates, USA
• Samuel Fung, IBM, USA
• Gennady Gildenblat, Pennsylvania State University, USA
• Dirk Klaassen, Philips Research Laboratories, The Netherlands
• Kwyro Lee, Korea Advanced Institute of Science and Technology, Korea
• Serge Luryi, State University of New York at Stony Brook, USA
• Marco Mastrapasqua, Agere Systems, USA
• Colin McAndrew, Motorola, USA
• Mitiko Miura-Mattausch, Hiroshima University, Japan
• Andrea Pacelli, State University of New York at Stony Brook, USA
• Roberto Suaya, Mentor Graphics, France
• Josef Watts, IBM, USA
• Xisheng Zhang, Celestry Design Technologies, USA
• Xing Zhou, Nanyang Technological University, Singapore

• Challenges of Modeling VLSI Interconnects in the DSM Era

Narain Arora, Simplex Solutions, USA
• Detailed Comparison of the SP, EKV, and BSIM3 Models

Peter Bendix, LSI Logic, USA
• Standardization and Validation of Compact Models

Britt Brooks, Texas Instruments, USA

• Advanced Surface-Potential-Based Model (SP)

Gennady Gildenblat, Pennsylvania State University, USA
• Engineering BSIM for the Nano-Technology Era and Beyond

Mansun Chan, Hong Kong University of Science and Technology, Hong Kong
• The Foundations of the EKV MOS Transistor Charge-Based Model

Christian Enz, Swiss Center for Electronics and Microtechnology, Switzerland

• The EKV Compact MOS Transistor Model Version 3: Accounting for Deep-Submicron Aspects

Matthias Bucher, National Technical University of Athens, Greece
• RF Applications of MOS Model 11

Dirk Klaassen, Philips Research Laboratories, The Netherlands
• HiSIM: Self-Consistent Surface-Potential MOS-Model Valid Down to Sub-100nm Technologies

Mitiko Miura-Mattausch, Hiroshima University, Japan
• Starting Over:  gms/Id-based MOSFET Modeling as a Basis for Modernized Analog Design Methodologies

Daniel Foty, Gilgamesh Associates, USA

• A Unified Process-Based Compact Model for Scaled PD/SOI and Bulk-Si MOSFETs

Jerry Fossum, University of Florida, USA
• Measurements and Modeling of Mobility in Ultra-Thin SOI

Marco Mastrapasqua, Agere Systems, USA
• RF MOS Noise Parameter Extraction and Modeling

Jamal Deen, McMaster University, Canada

• RF CMOS Modeling and Parameter Extraction Approaches Taking Charge Conservation into Account

Kwyro Lee, Korea Advanced Institute of Science and Technology, Korea
• Automatic Generation of RF Compact Models from Device Simulation

Serge Luryi and Andrea Pacelli, State University of New York at Stony Brook, USA
Part I: Motivation and methodology (by Serge Luryi)
Part II: Implementation and applications (by Andrea Pacelli)

• Xsim: A Compact Model for Bridging Technology Developers and Circuit Designers

Xing Zhou, Nanyang Technological University, Singapore
• Unified Statistical Modeling for Circuit Simulation

Colin McAndrew, Motorola, USA
• The Role of TCAD in Compact Modeling

Michael Duane, Applied Materials, USA

• Interconnect Modeling for High Speed Digital Circuits - the Role of RLC Coupling

Roberto Suaya, Mentor Graphics, France
• How to Build an SOI MOSFET Compact Model without Violating the Laws of Physics

Josef Watts, IBM, USA
• Simulation Study of Non-Quasi Static Behaviour of MOS Transistors  (contributed)

D. V. Kumar, M. B. Patil, and V. R. Rao, Indian Institute of Technology - Bombay, India

• Present Status and Future Direction of BSIM SOI Model for High-Performance/Low-Power/RF Application

Samuel Fung, IBM, USA
• A New Analytical Model of Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) Current Suitable for Compact Modeling  (contributed)

L. Larcher and P. Pavan, Università di Modena e Reggio Emilia, Italy
• Compact Model for Manufacturing Design and Fluctuation Study  (contributed)

K. Y. Lim and X. Zhou, Chartered Semiconductor Manufacturing Ltd., Singapore
• Physically-Based Approach to Deep-Submicron MOSFET Compact Model Parameter Extraction  (contributed)

S. B. Chiah, X. Zhou, K. Y. Lim, A. See, and L. Chan, Nanyang Technological University, Singapore

Narain Arora, Simplex Solutions, USA

• Peter Bendix, LSI Logic, USA
• Britt Brooks, Texas Instruments, USA
• Mansun Chan, Hong Kong University of Science and Technology, Hong Kong
• Christian Enz, Swiss Center for Electronics and Microtechnology, Switzerland
• Daniel Foty, Gilgamesh Associates, USA
• Gennady Gildenblat, Pennsylvania State University, USA
• Dirk Klaassen, Philips Research Laboratories, The Netherlands
• Mitiko Miura-Mattausch, Hiroshima University, Japan

B) 19:45 - 20:30:
Panel discussion on the selected 8 topics (average ~10min/topic).  Panelists are to provide their views on the pros and cons, supporting or opposing arguments for the following topic categories:

1. Compact model standardization vs. diversity
2. Compact model quality: definitions and priorities
3. Compact model applications in circuit design and technology development
4. Compact model parameter extraction vs. optimization
5. Compact model predictability and scalability
6. RF/parasitic/interconnect models vs. intrinsic transistor compact models
7. Compact model accuracy and efficiency tradeoff
8. Physically based vs. largely empirical compact models

• Model Equations of the Self-Consistent Surface-Potential MOS-Model HiSIM
  Mitiko Miura-Mattausch, Hiroshima University, Japan
• Submicron Circuit Design with BSIM3/4
  Mansun Chan, Hong Kong University of Science and Technology, Hong Kong
• MOS Transistor Modeling for RF IC Design
  Christian Enz, Swiss Center for Electronics and Microtechnology, Switzerland
• MOS Modeling, Design Quality, and Modern Analog Design
  Daniel Foty, Gilgamesh Associates, USA
• An Introduction to MOS Model 11
  Dirk Klaassen, Philips Research Laboratories, The Netherlands

S. B. Chiah, Physically-Based Approach to Deep-Submicron MOSFET Compact Model Parameter Extraction
D. V. Kumar, Simulation Study of Non-Quasi Static Behaviour of MOS Transistors
L. Larcher, A New Analytical Model of Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) Current Suitable for Compact Modeling
K. Y. Lim, Compact Model for Manufacturing Design and Fluctuation Study